Table of Contents

Overview

The MU CPU 2006 is based on the design sketched out by Charles Petzold in chapter 17 of the book CODE. I have modified the design a bit so as to implement it on a Softronics, Inc., Multimedia Logic simulator.

The computer has an 8-bit data bus and an 8-bit address bus limiting the addressable memory space to just 256 bytes. The CPU understands the 12 instructions described in Petzold's book including: load, store, add, subtract, add with carry, subtract with borrow, jump, jump on zero, jump on carry, jump if not zero, jump if not carry, and halt. The CPU lacks I/O devices. However, the state of the Program Counter, Instruction Register, Address Register, Data Bus, Accumulator, Carry Flag, and Zero Flag, and each step of the timing circuit are shown using seven segment displays and LEDs. Programs and data are preloaded into RAM by double-clicking on the MMLogic RAM element and specifying the path to the hexadecimal machine code text file that you wish to execute.

How It Works

The following block diagram gives the overall layout of the computer design. Each of the blocks is one component of the computer. Each block typically corresponds to one or more pages of the final MMLogic circuit. This diagram does not show the detailed control signals but rather just gives a high-level overview.

Let's trace through part of a simple program to see how this cycle works. As you trace through the code below also follow the block diagram above. There are three main parts to the instruction cycle on this machine. First, it fetches a byte from memory and places it in the Instruction Register (latch). Second, it fetches the next byte from memory and places it in the Address Register (latch). Finally, it executes the instruction.

Consider the following assembly language program that will endlessly count from 00 to FF. The Address column gives the location where each byte of the program will be placed in the RAM memory. The Data column contains the machine code itself -- this is the only part the computer really needs, the rest is for us humans. The Instruction column contains the assembly language mnemonic codes and data. The Comment column contains comments to better explain the program.

When the computer first starts running, the program counter (PC) is at zero.

Instruction 1: LOD A, [06h]

Load the value located at address 06 (hexadecimal) into the Accumulator.

Step 1: The Program Counter value 00 flows through the 2-to-1 Selector and onto the address bus. Address 00 lies within the memory space of the RAM module. The RAM module contains 10 (the LOD instruction) at address 00. It places the 10 on the data bus, sending this value back into the CPU. The value is latched by the Instruction Latch. The Program Counter increments.

Step 2: The Program Counter value 01 flows through the 2-to-1 selector and onto the address bus. Address 01 lies within the memory space of the RAM module. The RAM module contains 06 (a memory address) at address 01. It places the 06 on the data bus, sending this value back into the CPU. The value is latched by the Address Latch this time. The Program Counter increments.

Step 3: The CPU executes the load instruction. It does this by switching the top 2-to-1 Selector so that the Address Latch value (06) flows through the Selector and onto the Address bus. Address 06 lies within the memory space of the RAM module. The RAM module contains 00 (a data value) at address 06. It places the 00 on the data bus, sending this value back into the CPU. The value flows down into 2-to-1 Selector below the ALU where it is then routed into the Accumulator. The Accumulator then latches this 8-bit value.

Instruction 2 - ADD A, [07h]

Add the number located at memory address 07 to the number already in the Accumulator and store the result back into the Accumulator.

Step 1: The Program Counter value 02 flows through the 2-to-1 selector and onto the address bus. Address 02 lies within the memory space of the RAM module. The RAM module contains 20 (the ADD instruction) at address 02. It places the 20 on the data bus, sending this value back into the CPU. The value is latched by the Instruction Latch. The Program Counter increments.

Step 2: The Program Counter value 03 flows through the 2-to-1 selector and onto the address bus. Address 03 lies within the memory space of the RAM module. The RAM module contains 07 (a memory address) at address 03. It places the 07 on the data bus, sending this value back into the CPU. The value is latched by the Address Latch this time. The Program Counter increments.

Step 3: The CPU executes the ADD instruction. It does this by switching the top 2-to-1 Selector so that the Address Latch value (07) flows through the Selector and onto the Address bus. Address 07 lies within the memory space of the RAM module. The RAM module contains 01 (a data value) at address 07. It places the 01 on the data bus, sending this value back into the CPU. The value flows down into the left side of the ALU. The current value in the Accumulator flows into the right side of the ALU. The two numbers are added and the result flows down through the lower 2-to-1 Selector where it is latched by the Accumulator.

Instruction 3 - JMP 02h

Jump to address 02 and continue to execute instructions from that location.

Step 1: The Program Counter value 04 flows through the top 2-to-1 selector and onto the address bus. Address 04 lies within the memory space of the RAM module. The RAM module contains 30 (the JMP instruction) at address 04. It places the 30 on the data bus, sending this value back into the CPU. The value is latched by the Instruction Latch. The Program Counter increments.

Step 2: The Program Counter value 05 flows through the top 2-to-1 selector and onto the address bus. Address 05 lies within the memory space of the RAM module. The RAM module contains 02 (a jump to address value) at address 05. It places the 02 on the data bus, sending this value back into the CPU. The value is latched by the Address Latch this time. The Program Counter increments.

Step 3: The CPU executes the jump instruction. It does this by sending the Address Latch value directly into the Program Counter. The Program Counter is then set to be this new value. Therefore, the next instruction will be loaded from address 02. The computer will continue to repeat this sequence of steps forever--an infinite loop. As it does so, the value in the accumulator will count up to FF and then start over again at 00.

How-to-Run this Program

You must load a program into RAM before you try to run the CPU, otherwise the MMLogic program will crash. Load a program by double clicking on the RAM object on page 3 of the CPU circuit and click Browse. Find a machine code program file and select it.

In order to load this program into the RAM, we must use a text editor like NotePad to enter the numbers in the Bytes column in sequence as shown below. This is a machine code file. It contains only the instruction codes and data needed by the computer in order to execute that program. Save this as a .txt file (perhaps ex1.txt). Fire up the MMLogic simulator and load in the CPU circuit. Double click on the RAM device on page 3 of the CPU circuit to access the Memory Properties dialog. Click Browse and find this file (ex1.txt) and select it. Make sure the ASCII Hex radio button is selected as well. Click Ok to exit the dialog box and return to page 1 on the simulator to test your program.

10
06
20
07
30
02
00
01

Start the simulator running and flip the Run switch on the CPU page 1 control panel. If it does not quite work right you may need to double click on the timer object and adjust the settings. A number around 100 milliseconds usually works well. However, on a fast computer it will easily run with a 1 millisecond clock pulse.

Hardware Details

MMLogic organizes a complex design as a series of pages. The MU 2006 CPU required 13 pages of circuitry (however 2 pages are blank for future expansion). This section will discuss each page of the implementation. It would be helpful to download and view the CPU while you are reading the rest of this document. You can download the entire CPU circuit and test software in the Downloads section of this report.

Circuit Page 1 - The Control Panel

This is the main page we work from when running the CPU.

The top row of the control panel contains five sets of displays that show the status of the Program Counter (PC), Instruction Register (IR), Address Register (AR), Input Data Bus (DB), and the Accumulator Register (ACC). The two LEDs on the top right show the current value of the Carry Flag and the Zero Flag. The Carry Flag is set to 1 when a carry occurs in the ALU. The Zero Flag is set to 1 whenever the Accumulator contains the value zero. By carefully monitoring these displays we can have a good idea of what is happening inside the CPU as each instruction is executed.

On the lower right side of the control panel there are several switches and the timer. By double clicking the timer object we can set the speed at which the CPU operates. A delay between 20 and 100 milliseconds seems to work well. The Run switch is flipped (after the simulator is started and the RAM loaded with a program) to start the CPU running through its program at full speed. With the Run switch off, we can press the Step switch to single-step through the program one clock-tick at a time. This is useful in debugging a program. Finally, the reset switch, will reset the program counter to zero and start executing the program over from the beginning (however, not all registers are reset to zero so it is usually best just to stop the simulation and restart it).

To the left of the three switches there is a vertical column of LEDs. These show where we are in the instruction cycle. To the far left of the screen are a stack of LEDs. These light up to indicate which instruction is currently being executed.

Circuit Page 2 - The Timer Circuitry

This circuit is very similar to the one we did in an earlier assignment. The timing sequence has been modified somewhat. There are 6 full clock cycles required to execute one instruction. At the start of the 7th clock cycle the counter is immediately reset and cycle 1 starts over. Each cycle can be broken down into two parts using the Tic and Toc signals. This is critical for some longer instructions where we must first do one action and then follow it with another action while keeping all of the control signals set a certain way.

Circuit Page 3 - The External RAM

Notice that this CPU only has 8 address lines. This implies that this CPU supports a maximum of 256 bytes (2^8). This is the size of a single MMLogic RAM module. It turns out the 256 bytes is plenty of room for the programs we will be writing.

As mentioned earlier, page 3 is where we load our program into RAM. If we forget this step, the MMLogic program will crash.

Circuit Pages 4 & 5 - Reserved for Future I/O Devices

These are blank for this version of the CPU.

Circuit Page 6 - The Instruction Register

This latch holds the byte read in from RAM on machine cycle one. This should be an instruction telling the computer to do something. For an 8-bit instruction we could have up to 256 different instructions. To get those, you would have to add additional logic here to decode each byte. I used the 12 opcodes given by Petzold's CODE book. I use 3-to-8 Demultiplexers (Decoders) to decode the instruction. Since each instruction starts with a 1h, 2h, 3h, or Fh, I decoded those using one 3-to-8 Demultiplexer. Then I ran the outputs from there into the Enable input of 3 lower 3-to-8 Demultiplexers. These deal with decoding the lower nibble of the instruction byte. Taken together, this circuit ensures that control signals will be sent out only for the selected instruction. The hexadecimal instruction op codes are given below.

Circuit Page 7 - The Address Register

The address register is a latch that holds the 2nd byte read in.

Circuit Page 8 - The Arithmetic Logic Unit (ALU)

Here I cheated a bit and used the ALU provided in the MMLogic toolbox. I am only using a few of its many features. This is just a fancy adder.

Circuit Page 9 - The 2-to-1 Selector Circuit #1

This 2-to-1 Selector circuit appears at the top of the block diagram shown at the beginning of this document. It selects between the Address Register (Latch) and the Program Counter. The output from this circuit is the computer's Address Bus.

Circuit Page 10 - The 2-to-1 Selector Circuit #2

This 2-to-1 Selector circuit selects between the ALU output and the input data bus. The output from this circuit goes into the Accumulator.

Circuit Page 11 - The Accumulator

The Accumulator is also known as register A. It is a latch that holds a data value or the result of a calculation. Many of the instructions operate on the contents of this register. More advanced CPU's will have additional general purpose registers. Our little CPU only has this one.

Circuit Page 12 to Page 13 - The Program Counter

This device is based on eight D-type edge-triggered flip-flops with preset and clear. It always contains the address of the next piece of data to be fetched from memory. Typically it is incremented sequentially. However, jump-type instructions can load the program counter with a new and different value. This is the key feature that let's us implement selection (if-then-else) and looping (for and while) instructions. Page 12 is wired using 6 NOR gates to construct a single flip-flop as we used to wire it (early versions of our logic simulator did not have this type of flip-flop in the tool palette). Page 13 contains the 7 additional flip-flops wired using the new pre-built flip-flop object. Together, these two pages give us an 8-bit program counter.

Downloads

MU 2006 CPU Circuit

Example 1 Counter Program